Keysight Introduces First DDR5 and LPDDR5 Memory Protocol Debug and Validation

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The Performance Overview provides graphical and summary calculations of Read, Write, and Total MByte data rates along with a calculation and graph of the percentage of bus utilization.

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Transaction decode provides a high-level view of the memory protocol transactions. This condensed view makes it easy to step through the memory traffic flow.

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This tab displays the details of a selected memory transaction and all other transactions in the same sequence or ‘open/closed page’. ‘Pages’ open with Activate commands, all Reads or Writes associated with the same Rank, Bank Group, Bank, and Row Address are part of the ‘open page’. Pages close with an associated Precharge. When either a Read or Write transaction is selected, the Data associated with the selected Read or Write is also displayed with the associated address.

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The traffic overview containing a graphical view of transaction decode with summary calculations and meta-data provides a condensed and insightful overview of system activity and enables powerful navigation to areas of interest.

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All of the analysis views can be locked, tiled, or docked to fit the individual users requirements. 1024 global markers track across the different views.

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